1. Field of the Invention
The present invention relates to a clock data recovery circuit, and more particularly, to a clock data recovery circuit which extracts clock information and data information from the transmitted data in a burst mode.
2. Description of the Related Art
With a recent wide spread of a high speed chip-to-chip communication method such as Gigabit Ethernet, IEEE1394, and USB 2.0, a demand increases for an SER/DES (serializer/deserializer) design for converting high speed serial data transmitted via a cable to low speed parallel data which is easy to process. In a typical chip-to-chip communication, a clock signal is not separately transmitted while data only is transmitted through a communication channel. Accordingly, to process data synchronized with clock, a clock data recovery (CDR) circuit to extract clock information and data information from the transmitted data at a receiving end is needed.
In particular, in a plesiochronous system using a clock source at each of transmitting and receiving ends such as a passive optical network (PON) and ATM, and SDH/SONET, the CDR circuit having a fast lock time is necessary for processing asynchronous data transmitted in a packet format.
FIG. 1A is a block diagram illustrating the configuration and operation principle of a conventional burst mode clock data recovery (CDR) circuit in which two gated-voltage controlled oscillators (GVCOs) operating in parallel are used. The conventional technology is described below with reference to the circuit diagram of FIG. 1A and a timing diagram of FIG. 1B.
An input signal Din and an inversed signal of the input signal Din are input to GVCOs 110 and 111, respectively. Another input of each of the GVCOs 110 and 111 is a control voltage output from a phase locked loop (PLL) (not shown). The first GVCO 110 generates an output signal Clk1 having a predetermined cycle when the input signal Din is maintain to be “low” as shown in the timing diagram of FIG. 1A. The second GVCO 111 generates an output signal Clk2 having a predetermined cycle when the input signal Din is maintain to be “high”.
While passing through a NOR gate 113, the signals Clk1 and Clk2 are synchronized with the input signal Din and converted to a clock signal Cout having a very constant cycle. As the clock signal Cout is applied to a D-flipflop (D-F/F) 114 as a clock input, an output signal Dout of the D-F/F 114 becomes a signal that is generated by making the input signal Din synchronized with the clock signal Cout.
In other words, FIG. 1A shows a method of extracting the clock synchronized with data by extracting oscillating time points of the GVCOs 110 and 11 using the input data.
However, since each of the receiving and transmitting ends uses a separate clock source in the plesiochronous system, clock frequencies of the receiving and transmitting ends are different to a degree. Accordingly, a phase error is continuously accumulated due to a difference in a bit rate with respect to continuous input of DC data.
As a result, in the conventional CDR circuit based on the GVCO as shown in FIG. 1A, the maximum data bit number to be transmitted without transition is greatly restricted by the difference in the bit rate between the transmitting and receiving ends.
To improve the above drawbacks, a larger amount of transition needs to be applied to the transmitted data. A technology of using an encoding block such as 8B/10B at the transmitting end is a typical method for this purpose. The 8B/10b technology is a sort of data encoding technologies used for data transmission in a 10 gigabit Ethernet technology used for a back-bone such as LAN.
FIG. 1C shows the configuration of a conventional burst mode CDR circuit and the principle of operation thereof, in which T/4 delay lines 130 and 131 are added to remove a high frequency noise in recovered clock. That is, to remove the high frequency noise or glitches occurring in the recovered clock due to the difference in the bit rate, the oscillation time point of the GVCO is controlled using the input data Din and the T/4 delay lines 130 and 131.
The operation of the circuit is described with reference to a circuit diagram shown in FIG. 1C and a timing diagram shown in FIG. 1D.
The oscillation time point of the GVCO2 is controlled by the input data Din and T/4 delayed data. When these data are all “low”, a clock signal Clk2 that is inversed every T/2 of a clock cycle is generated. When any one of the data is “high”, the clock signal Clk2 is maintained to be “high”.
Likewise, the inversed signal and the T/4 delayed signal of the input data Din control the oscillation time point of the GVCO1. When both signals are “high”, the signal Clk1 is inversed every T/2. If any of the signals is “low”, the signal Clik1 is maintained.
When the signals Clk1 and Clk2 respectively generated by the GVCO1 and the GVCO2 pass through a NAND gate, the clock signal Cout having a cycle T is synthesized and the synchronism of the output clock is characteristically maintained by the input data. In this case, since the amount of delay by the T/4 and T/2 delay lines is determined by a VCO control voltage vcont of the PLL at the receiving end, the T/4 and T/2 delay lines operate regardless of the bit rate of the transmitting end. Thus, in a method of using the T/4 delay element, as shown in FIG. 1A, even when a high frequency noise can be removed within a predetermined range, the allowance range is limited to several percentages.
FIGS. 2A and 2B show that, in the conventional burst mode CDR circuit, a difference in the bit rate and input jitter affect the determination of the maximum DC data bit number to be transmitted. The amount of jitter existing in the transmitted data is indicated by ±φj and it is assumed that data sampling is performed at a falling edge of a clock at the receiving end.
FIG. 2A shows a case in which the bit rate fT at the transmitting end is higher than the bit rate fR at the receiving end (fT>fR). When N-bit DC data is transmitted from the transmitting end, a phase error corresponding to a difference in the bit rate between the transmitting end and the receiving end is accumulated every clock. To accurately receive the N bits without error at the receiving end, at least the N-th falling edge of the clock at the receiving end must be anterior to the time point of (the N-th bits−φj) of the transmitted data. That is, the maximum DC data bit number to be transmitted without error can be expressed in Inequality 1. However, it is assumed that 50% duty of the clock at the receiving end is guaranteed.
                                          N            -            0.5                                f            R                          <                              N            -                          Φ              j                                            f            T                                              [                  Inequality          ⁢                                          ⁢          1                ]            
Unlike FIG. 2A, FIG. 2B shows a case in which the bit rate fT at the transmitting end is lower than the bit rate fR at the receiving end (fT<fR). To receive the N-bit DC data without error at the receiving end, in the worst case, the (N+1)th falling edge of the clock at the receiving end must be posterior to the time point of (the N-th bits+φj) of the transmitted data. That is, the maximum DC data bit number to be transmitted without error can be expressed in Inequality 2.
                                          N            +            0.5                                f            R                          <                              N            +                          Φ              j                                            f            T                                              [                  Inequality          ⁢                                          ⁢          2                ]            
From Inequalities 1 and 2, the maximum DC data bit number to be transmitted can be expressed in Inequality 3 that is a formula with respect to the input jitter φj and the bit rate difference fdijf.
                                          N            MAX                    <                                    1                              2                ⁢                                  f                  diff                                                      -                          (                              1                -                                  2                  ⁢                                      Φ                    j                                                              )                                      ,                              wherein            ⁢                                                  ⁢                          f              diff                                =                                                                                    f                  T                                -                                  f                  R                                                                                  f              T                                                          [                  Inequality          ⁢                                          ⁢          3                ]            
As shown in Inequality 3, the maximum DC data bit number to be transmitted logarithmically decreases as the bit rate difference increase and linearly decreases with respect to the input jitter.
Under a lossy channel environment such as USB 2.0 or Serial ATA, since allowable input jitter approaches 40%, it is still difficult to adopt the method shown in FIG. 1B. For this reason, the burst mode CDR circuit has been used for optical communication such as PON. For the lossy copper channel, a CDR circuit in a tracking manner using the PLL or the CDR circuit in an over-sampling manner has been used.
However, since the burst mode CDR circuit has merits such as a fast lock time and simple hardware structure, studies to use the burst mode CDR circuit in the lossy channel environment has been made.
The conventional burst mode CDR circuit using the GVCO has the following problems.
First, when the data transmission rate difference exists between the transmitting end and the receiving end, as the DC input data continuously transmitted, jitter is accumulated in the recovered clock so that the maximum DC data bit number to be transmitted is restricted. When the data transmission rate difference exists between the transmitting end and the receiving end affects the operation of the CDR circuit, the bit number of the output data may increase or decrease compared to that of the input data as shown in FIGS. 3A and 3B.
FIG. 3A shows a case in which fR is greater than fT (fT<fR). As a result, a binary “1” is inserted in the output data Dout compared to the input data Din, which cases an error. FIG. 3B shows a case in which fR is less than fT (fT>fR). As a result, a binary “1” is lost from the output data Dout compared to the input data Din, which cases an error.
Second, the received data includes a great amount of jitter due to the ISI by the channel, the jitter by a power driving circuit at the transmitting end, the jitter of a clock generator at the transmitting end, and the jitter by a receiving circuit, so that errors can be generated in the recovered clock and data.
Third, unnecessary glitches are generated during the synthesis of the recovered clock due to mismatch between rising time and falling time of a VCO clock that generated when the gated-VCO constituting the burst mode CDR circuit is turned on/off. When the width of the glitch increases enough to be recognized by a CMOS circuit, a data receiving error is generated.
Fourth, in the conventional burst mode CDR circuit, the input data and the inversed information of the input data are used as the control signals to control the oscillating time points of the two VCOs operating in parallel. Thus, the result of mismatch between the VCOs is reflected in recovering the clock so that performance of the CDR circuit may be deteriorated.